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I am studying for a end of semester exam and am confused with the following question. If a CPU has a 16bit address bus and 8 bit words, how much memory in KB's can it address? My understanding would tell me that it can address 64KB, however to do this I just used 2 ^ 16 = 65,536. That calculation never actually took into account 8 bit words so I am not sure if it is correct. Also what does 8 bit words mean?

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    You used it indirectly: the total amount of addressable memory is 2 ^ 16 * 8 bits. Since one byte = 8 bits, that's 2 ^16 bytes, i.e. 65536 bytes, or 64 KiB. Note that K is the SI prefix for 1000. If you mean 1024, use Ki.
    – jcaron
    Jun 6, 2017 at 9:31
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    Mind the difference between SI prefix kilobytes (1,000 bytes) and binary prefix kibibytes (1,024 bytes). 2^16 = 65,536 = 64 kibi ~ 65.5 kilo. The answer sought is probably one where kilo is taken to mean kibi, but there are times when the difference really matters. If you want to be completely certain, take the safe route and specify the number of bytes, and offer translation into more handy units such as kilobytes or kibibytes as a convenience for your teacher. Compare Wikipedia: Binary prefix. Memory chips typically specify eg 65,536x8 bits.
    – user
    Jun 6, 2017 at 14:19
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    Possible duplicate of How many memory addresses can we get with a 32-bit processor and 1gb ram?
    – gronostaj
    Jun 6, 2017 at 19:30
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    I presume you assume no bank swapping. Most 16 bit CPUs use some form of bank swapping that makes this really hard to answer.
    – Joshua
    Jun 6, 2017 at 21:34
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    @MichaelKjörling The question say KB which has always meant 1024 bytes.
    – kasperd
    Jun 7, 2017 at 5:32

5 Answers 5

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A word, in the majority architectures, is the largest piece of data that can be transferred to and from the working memory in a single operation.

The largest possible address size, used to designate a location in memory, is typically called a hardware word.

So, your CPU will be able to address 64KB (2^16) but will only be able to transfer in a single operation 8 bits.

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    I'm sure this answer is the one the teacher is after, but is it actually correct? Could you not use something like PAE to allow a 3 level hierachy (or even more) to allow CPU's to access more then 64KB? I'm not a hardware expert, but didn't the Commodore 128 even manage to do something like this on an 8 bit word, 16 bit bus by allowing switching of RAM banks ?
    – davidgo
    Jun 6, 2017 at 9:09
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    Not quite sure I understand your sentence "will only be able to transfer in a single operation is 256B (2^8)"? It can only ever transfer 1 word = 1 byte = 8 bits in a single operation.
    – jcaron
    Jun 6, 2017 at 9:29
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    @davidgo still PAE requires the address bus to be sized appropriately. Intel CPUs supporting PAE have an address bus of 36 bits.
    – Dmitry Grigoryev
    Jun 6, 2017 at 9:46
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    PAE is more or less a brand/feature name specific to modern x86 CPUs. Yes, schemes to indirectly address larger amounts of memory have been implemented for ages (eg XMS), these in the end treat the memory subsystem like a peripheral that can be reconfigured constantly to expose different memory into a smaller address space. Also, see the segmented memory model of old school x86...
    – rackandboneman
    Jun 6, 2017 at 10:01
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    @Overmind you should clarify your answer a bit. No-one really uses a single B as a unit and the reason is exactly what's happened here - you're confusing bits and bytes. The OP states "8-bit words* - each word therefore has 8 bits (1 byte) and can only transfer that in one operation. 256 is simply the number of possible values each word has, not how much is transferred.
    – adelphus
    Jun 6, 2017 at 10:42
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A machine word, or commonly just word is the largest unit of data that the CPU can manipulate as a whole using common instructions. This has nothing to do with memory addressing.

What matters is the unit of address resolution, which is commonly an 8-bit byte even on 16/32/64 bit architectures. It doesn't have to be equal to the machine word size, but it probably is in your case.

An 8-bit addressable unit combined with 16-bit address bus amounts to 64KiB of RAM that the CPU can address.

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    But I have used machines where the unit of address resolution was 16 bits. (So the concept is meaningful.)
    – Martin Bonner supports Monica
    Jun 6, 2017 at 12:25
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    @MartinBonner Nevertheless, it is not directly related to the CPU word size.
    – glglgl
    Jun 6, 2017 at 15:10
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    @glglgl - It's very related. I don't believe there are any architectures that don't have an address unit of either 8 bits or their word size.
    – Jules
    Jun 7, 2017 at 1:07
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    I disagree with the statement that a word is the largest unit that the CPU can manipulate as a whole. The Intel i7 has a 64 bit data bus and can still use 256 bit SIMD instructions. If Wikipedia is correct, then word refers to the data bus width and not to CPU internal stuff.
    – Thomas Weller
    Jun 7, 2017 at 5:30
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    @ThomasWeller: 8088 has 8 bit data bus, but still a 16-bit instructions. In fact it is a 8086 with a smaller databus. Note: the width of databus and the actual transfer is also different (think misaligned data).
    – Giacomo Catenazzi
    Jun 7, 2017 at 16:15
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Also what does 8 bit words mean?

In context, the word size goes with the address size to describe the memory bus. There are 16 bits gling out to the memory so it can choose 64ki locations. Then, each location contains 8 bits.

The word size here may or may not match the CPU computation unit size, and this may or may not match the logical granularity in addressing.

For example, a CPU may advertise a 16-bit bus (for this purpose). It uses 16-bit addresses in its instructions, and like your example has 64ki. But it has 15 bits of address bus and 16 bits of data bus. It only needs 32ki addresses and always gets 2 bytes with each location. (If an instruction wanted 1 byte, it would dispatch the address with the least bit missing, fetch both bytes in that step, then look at the least bit of the desired address to decide which half to use.)

Note that bank switching, PAE, etc. mentioned by others are not relevant here. A memory management unit might use 16-bit addresses and have 20-bit hardware address, so the CPU needs to switch and map things to make use of the actual 20-bit address range of RAM chips that can be addressed.

Be sure to specify units in your answers. “64ki”. Of what? 8-bit words, making it (still) 64ki bytes of addressable RAM. That step eliminates confusion and makes problems like this trivial.

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You have to use word size in calculations as well. The answer is 64 KB.

You can address 2^16 words and each word is 8 bit (= 1 byte). Therefore it is 64 KB.

If the word size was 16 bit. The answer would be 128 KB.

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    Your calculation doesn't hold for common 32-bit CPUs which still can address 2^32 bytes of memory (4GB), not (2^32)*4 (16GB).
    – Dmitry Grigoryev
    Jun 7, 2017 at 8:53
  • Modern CPUs address larger “rows” and have fewer address lines to match. The question speaks of address bus the physical side of things. So multiplying by the word size of that bus (not the CPU register size) is correct.
    – JDługosz
    Jun 7, 2017 at 9:20
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There are two sides to this, what your instructor probablly wants you to tell him and what the reality is.

First what your instructor probablly wants you to tell him.

"16 bits can address 2^16 memory locations, each location is 8 bits. So we can address a 524288 bit (65536 octet) memory."

This however reflects a rather oversimplified worldview. The reality is more complicated and to give a definitive answer requires more information. Some of the ways in which real systems can be more complicated than this include.

  • Many processors do not have a dedicated IO map, so parts of the memory address space may need to be used for things other than memory.
  • The "word size" of the processor is not nessacerally the same as the width of the memory data bus or the smallest addressable unit of memory.
  • Some busses allow the movement of varying size data units. This requires further addressing which may or may not be handled by bits of the main address bus.
  • Some busses multiplex different signals on the same lines. For example SDRAM uses the same address lines twice to send a "row address" and a "column address".
  • Many systems used bank switching approaches to allow programs to access more memory than the processor could natively address.
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