On x86 PCs, the memory space is shared in the system. System memory maps from the bottom up (0 -> xGB) & PCI memory space is in the upper part of system memory space (xxx --> FFFFFFFF 4GB-1). Note that "memory space" is not "memory". It's just address ranges for HW to decode & claim transactions.
This is usually ok because PCI/PCIe devices generally request a reasonable amount of memory for their PCI BAR (Base Address Range), such as 64K or less. BARs are where things like device-specific registers reside and what a device driver would access to control the device. Very large BARs don't apply to most devices because they use DMA engines to transfer data instead of the host CPU performing PIO accesses (very poor performance), so they don't need to map their internal storage to BARs.
Once you start using GPU type devices, for example, the higher end ones request very large PCI BAR spaces, such as 32GB or more. If your PCI memory space is limited to 32-bit, then there's no available address range to fit 32GB in. So, BIOS PCI enumeration started to support 64-bit PCI BAR assignment during enumeration. This generally started about 12 years ago and some of the first algorithms to support it still had bugs or limitations. Some systems would hang if a BAR was larger than 8GB. PCI enumeration algorithms have improved since then.
So, the "Above 4GB decoding" means that the BIOS PCI enumeration is "allowed" to assign PCI BARs memory ranges above 4GB (32-bit max). It may even do that for small PCI BARs, as long as they report themselves as 64-bit.
Note that in PCI/PCIe devices, PCI BARs are 32-bit. If a PCI BAR wants to support 64-bit, it "combines" 2 32-bit BARs to store the 64-bit address. A device with "64-bit PCI BAR 2" means that its BAR 2 is low 32b of the assigned address & BAR 3 then becomes the upper 32b.
Also note that 32-bit x86 can still access PCI BARs above 4GB due to PAE.