Does anyone know what the Arbiter would look like on a DDR memory controller? I was thinking that in order to perform memory access operation reordering for optimisation it may contain a ROB / scheduler / retire like architecture perhaps... Does anyone have an insight into the actual implementation?

  • Are you looking for a mechanism to arbitrate memory requests between channels/Ranks...? – lol Nov 13 '19 at 19:17

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Browse other questions tagged or ask your own question.