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We have a system optimization problem that requires a clear workflow of the execution of a CPU. How does a modern CPU (e.g. Intel Xeon) with multiple levels of caches execute a program originally stored on a hard drive of a computer?

I know roughly the program is first loaded to memory, and then, the CPU decodes the instructions and get the data needed from the memory. But, What is the detailed workflow of a CPU loading instructions from DRAM with all possible level of caches involved (maybe from DRAM to the L3 cache, L2 cache and the L1 Instruction cache or directly from DRAM to the L1 Instruction cache), and the detailed workflow of CPU loading data (from DRAM to the L3->L2->L1D?).

closed as too broad by Ramhound, harrymc, music2myear, Kamil Maciorowski, fixer1234 Jul 9 at 22:02

Please edit the question to limit it to a specific problem with enough detail to identify an adequate answer. Avoid asking multiple distinct questions at once. See the How to Ask page for help clarifying this question. If this question can be reworded to fit the rules in the help center, please edit the question.

  • Thanks for reminding, but I do think this question is answerable and practical. Because right now we are facing a system optimization problem that requires a clear workflow of the execution of a CPU. – logan_white Jul 3 at 18:18
  • Realistically the workflow you describe is the same between an original 8086 and a Xeon released in 2019. Silicon might be faster, there might be additional instructions, but the architecture really hasn’t changed. – Ramhound Jul 3 at 18:49
  • Thank you @Ramhound, really appreciate it. Do you have some detailed documentation describing it? – logan_white Jul 4 at 0:57