Is the only purpose of transistors in a CPU to act as the switches that define its instruction set? And if so then why does increasing the number of transistors increase its speed?
Off the top of my head:
More cache, which is faster than RAM
More SIMD instructions, which process faster than single-data instructions
More cores, so you can do two or more things at once
Pipelines, so each core can do more things at once
Better processing logic, like more sophisticated branch prediction logic
If you're curious about this sort of thing I highly recommend the book The Elements of Computing by Noam Nisan and Shimon Schocken (at least the first half). After going through it you'd be able to answer your own question in great detail with a full appreciation of the parts involved.
The companion website actually has some sample chapters and notes. It's a very approachable book. I went through it on my own with no problem and then took a brand new class at my university that used it as its primary text.
Ken already summarized some of the reasons in his answer. To expand on that further
- More cache, which is faster than RAM
Obviously bigger caches need more transistors. But with more transistors we also have the choice of using faster caches. CPU caches are just SRAM which is typically made from 6 transistors (A.K.A 6T SRAM). However when there are enough transistors it may be worth using faster but bigger SRAM cells made from more than 6 transistors (such as 8T, 10T SRAM)
- More SIMD instructions, which process faster than single-data instructions
Not only SIMD but any type of accelerating instructions. For example modern architectures often have an AES unit for faster encryption/decryption, FMA for better mathematic computation (especially digital signal processing), or virtualization for faster virtual machines. Supporting more instructions means more resources are required to decode and execute them
These are quite clear
In the past there was not enough die area for the FPU so people must buy a separate one if they have high requirements of floating-point arithmetic. With significantly more transistors it's possible to have the FPU built-in, speeding up floating-point math a lot
Besides, modern CPUs are superscalar and will try to do multiple things at once by finding independent data pieces and calculate them earlier, even though the instruction stream is linear and serial. The more things they can do in parallel the faster they'll be. To do that a CPU can have multiple ALUs and an ALU can have multiple execution units. If for example a CPU has 5 adders compared to 4 in the previous generation then it's already running 25% faster in the most optimistic situation without any clock changes. More sophisticated CPUs even employ out-of-order execution (which is the case for most modern high-performance CPUs)
- Better processing logic, like more sophisticated branch prediction logic
Operations can typically be done in various ways. If you have more transistors you'll have more resources to use a faster technique. Some simple examples:
A simple shifter is made by serially connecting flip-flops together.
That needs just one flip-flop per bit, hence extremely compact. But it needs one clock to shift left or right one bit. That's why microcontrollers and small embedded CPUs have only instructions to shift by one. See
When you have more transistors to spend you can change to a barrel shifter. Now a CPU can shift bits in a single clock with the cost of hundreds or thousands of transistors
- A simple adder is also made by connecting full adders in series. This way an N-bit adder needs N clocks to finish its job, which is certainly not what people expect in a CPU
- With more transistors we can speed up the addition by pre-calculating the carries with carry-lookahead or carry-save adder. The full adders are still used, but a lot more space is needed for the the carry-precalculation unit
The same thing applies to other units like multipliers, dividers, scheduler... For example we can do a multiplication extremely fast in a single clock using combinational logic. You can see some simple examples in the question 3-bit multipliers - how do they work?. But the transistors needed will grow to the square of the input widths, therefore small CPUs with a multiplier use sequential logic instead to save a lot of space for the multiplier:
Older multiplier architectures employed a shifter and accumulator to sum each partial product, often one partial product per cycle, trading off speed for die area. Modern multiplier architectures use the (Modified) Baugh–Wooley algorithm, Wallace trees, or Dadda multipliers to add the partial products together in a single cycle. The performance of the Wallace tree implementation is sometimes improved by modified Booth encoding one of the two multiplicands, which reduces the number of partial products that must be summed
Once you have a huge pool of transistors you can even use combinational logic to do an FMA which is far more resource-intensive than a multiplier
Modern computers may contain a dedicated MAC, consisting of a multiplier implemented in combinational logic followed by an adder and an accumulator register that stores the result. The output of the register is fed back to one input of the adder, so that on each clock cycle, the output of the multiplier is added to the register. Combinational multipliers require a large amount of logic, but can compute a product much more quickly than the method of shifting and adding typical of earlier computers.