Say that a CPU wants to get a particular address in memory, it will place that address on the address bus. But will that address be visible to all RAM chips (and therefor all DIMMS) on the computer, or will only chips that contain the data required see this?
Not every line is passed to every chip, but there are enough lines that do to make it an important design consideration.
From the CPU there are some control and address lines that select particular DIMM modules, but the broad swathe of data and address lines are connected to all modules, from CPU to the first module and then the other. (Lines at the bottom and top, with a large "dot" denoting a connection point)
The address bus itself must be seen by every DRAM chip. From the picture above it gets routed onto the DIMM and passed through every chip, while simultaneously continuing on to the next module.
DRAM memory chips may well be able to be connect data lines directly to the host and indeed the data bus appears to be separated into "data lanes" per DRAM chip to host so that data lines (which by their nature are going to be at a higher rate than adress lines) is not passed to every chip on the module. They will still be seen by a module in another slot, but a single extra drain is better than many more.
For dual or higher channel systems you get more sets of data and control lines, a set per channel, but once you put two or more sticks on a channel you end up with the layouts above. A single stick per channel obviously limits all the signals to within one module.
Having each DRAM chip buffer and pass on the signal would be possible, but would increase the latency, especially at the end of the chain. They would also then not be UDIMMs (Unbuffered DIMMs)
Conversely fully buffered DIMMs get connected like this:
On older systems with a real bus, it works like Ethernet in the old days when all computers were connected physically to the same wire or medium--or the new days with wireless Ethernet--all systems on the same wire listen and receive all traffic. This would include RAM on that bus.
Similarly, all devices/chips on a given bus receive all traffic, but are only supposed to act on data meant for them. There's various schemes to make RAM only respond when it's addressed (Commodore 64 used a device called a PLA, other systems used other chips or 74LS chips) Chip level or bus level protocols are needed and used to make sure multiple devices don't talk at once; and they have to be followed--"collisions" on busses can cause the CPU to freeze or behave erratically (it's a device on the bus too).
RAM on modern CPUs is directly connected to specific pins on the CPU and is no longer on a bus (a 1-device bus is called a port). Modern hardware in general is moving away from a shared medium model. PCIe works more like switched Ethernet, SATA is point-to-point, and USB and other things go through controllers that are on PCIe.
PCI stands for Peripheral Component Interconnect--and that's a better name for the mechanism--interconnect--than bus these days. Again RAM is on its own ports.