This appears in lspci on my Dell XPS 13 9310:

0000:00:14.2 RAM memory: Intel Corporation Device a0ef (rev 20)

Does RAM work over PCIe now?

  • If it was a PCI device it'd show up in lspci and not lsusb. I'm not sure why it appears in the lsusb at all
    – QuickishFM
    Dec 10, 2020 at 19:23
  • @QuickishFM the information I found on the device was from lspci logs... it does appear underneath a USB controller, though I suspect it is alongside the USB controller rather than below it and is likely housed in the same package as the USB and Ethernet controllers on the motherboard.
    – Mokubai
    Dec 10, 2020 at 21:47
  • It was on lspci, I wrote it wrong
    – Paprika
    Dec 10, 2020 at 22:44

1 Answer 1


According to https://linux-hardware.org/?probe=ba53f6e513 the proper device name is Tiger Lake-LP Shared SRAM

The RAM as mapped into the memory region is also particularly small and so is unlikely to be used for anything more than sharing data between devices.

0000:00:14.2 RAM memory [0500]: Intel Corporation Device [8086:a0ef] (rev 20)
    Subsystem: Dell Device [1028:0991]
    Control: I/O- Mem- BusMaster- SpecCycle- MemWINV- VGASnoop- ParErr- Stepping- SERR- FastB2B- DisINTx-
    Status: Cap+ 66MHz- UDF- FastB2B- ParErr- DEVSEL=fast >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
    Region 0: Memory at 603f2e0000 (64-bit, non-prefetchable) [disabled] [size=16K]
    Region 2: Memory at 603f2ea000 (64-bit, non-prefetchable) [disabled] [size=4K]
    Capabilities: <access denied>

From the Intel® 300 Series and Intel® C240 Series Chipset Family Platform Controller Hub datasheet ISH Micro-Controller section:

ISH Micro-Controller

The ISH is operated by a micro-controller. This core provides localized sensor aggregation and data processing, thus off loading the processor and lowering overall platform average power. The core supports an in-built local APIC that receives messages from the IOAPIC. A local boot ROM with FW for initialization is also part of the core.


The local SRAM is used for ISH FW code storage and to read/write operational data. The local SRAM block includes both the physical SRAM as well as the controller logic. The SRAM is a total of 640 kbytes organized into banks of 32 kB each and is 32-bit wide. The SRAM is shared with Intel® CSME as shareable memory. To protect against memory errors, the SRAM includes ECC support. The ECC mechanism is able to detect multi-bit errors and correct for single bit errors. The ISH firmware has the ability to put unused SRAM banks into lower power states to reduce power consumption.

It is not "PCIE memory", but it is a memory device in the system that is accessible by other devices and therefore needs to be seen across the bus.

It is entirely possible that the majority of the memory is reserved for the microcontroller to work from, and that a small patch of memory is available for the system to read the captured sensor data.

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