A decade or two ago I could buy ECC (Error Correction Code) RAM for
PCs I assembled. ECC RAM provided SEC-DED, I guess from bit flips
caused by ionizing radiation (I don't know what else could cause
transient bit errors to pop up in RAM or I/O buses).
There are 3 general causes of bit errors, the first two of which are single event upsets:
Radiation (primarily free neutrons). This particular phenomenon is dependent on a number of things such as the neutron cross section of the particular device. It may seem counter-intuitive, but the newer much smaller geometries have a lower probability of an upset due to neutrons because they have been designed to be less susceptible. See the Xilinx link (from below).
Lead, specifically Pb210 which is part of the Uranium decay chain and is found in older kit in the balls of BGA devices. Xilinx refers to errors from this as the alpha rate as they emit an alpha particle during decay. Clearly not an issue for a great deal of current equipment that is lead free (but still quite an issue in aerospace where tin lead processing is still common).
General bit error rate issues. A memory interface is a communication channel, and all communications channels have an error rate. Admittedly, you may never see a single bit error in the life of a particular piece of equipment as this is a statistical quantity. Errors due to electrical noise and poor device decoupling also fall into this category.
i.e., if ECC RAM was considered a useful feature a decade ago, do the
reasons it was useful no longer apply to current personal computers
and servers? Or is the thinking now that ECC RAM was never actually
It was useful, but of limited value, although many side channel attacks can be mitigated by its use.
The real reason you can't find it in commercially available boards is simply cost and those boards that do have it have a rather large premium, far higher than the delta cost of the silicon to handle it and the extra 8 data bits (for a 64 bit memory system). The cost-benefit analysis doesn't support its broad availability.
I do remember a research paper from Boeing that discussed soft errors in a Denver data centre. The amount of free neutrons is (up to a certain level) proportional to altitude. The higher you go, the more there are.
If ECC memory was helpful twenty years ago presumably it would be more
helpful now that PCs are running with 1-2 orders of magnitude more
memory, at lower voltages and with smaller physical features that
(presumably) are more susceptible to corruption from stray radiation.
Are any of these assumptions incorrect?
The memory interfaces we have today are far more robust than you might think; for DDRx, the data strobes are differential (so they reject common mode noise) and lower transition voltages are actually better for high speed interfaces, as we proved years ago with ECL.
In avionics, and in particular flight safety critical avionics such as flight control computers, the use of ECC for L2 and beyond is mandatory as is the use of parity for L1. That is one of the reasons those cards are not from Intel or AMD.
[Update]. The specifics of just how memory cells are laid out has a rather large effect on their susceptibility to SEUs; Xilinx has taken a particular approach that effectively stacks memory cells in such a way that the probability of a high energy neutron causing a bit flip is significantly reduced.
As I am not an IC designer that is all I can really say. There is a great deal more information at the Rosetta Project.