In my notes, I keep coming across two terms which are confusing me while looking through my notes on the 8085 processor.

The first is address data multiplexing. What is meant by this exactly? I understand the concept of multiplexing (combining n signals to one), but where does the address data come into this?

Secondly, what is bus buffering? My understanding is that this is the amplification of electrical signals in the circuit so that they can travel longer distances. Is this correct?

  • Good question. Without delving too much into what Synetech inc. has answered below, note that the term buffering does not have anything to do with amplification of signals. Buffering is a way to effectively isolate two subsystems, regardless of the processes going on in either side of the bus. – Breakthrough Mar 15 '11 at 22:01
  • so how’d the test go? – Synetech Mar 28 '11 at 3:11

I tried to get my computer architecture text out, but it is buried in a box in the back.

Address multiplexing allows you to use fewer pins on the processor, and thus fewer bus lines. So instead of having some bus lines for the address, and some more for the data, you put the address on the data line, it gets read, then you put the data on the same lines, and it gets read and stored at the previously read address. For the 8085, it allowed the design to add one pin, but cut 8, for a net gain (loss?) of 7 pins (reduced physical/manufacturing complexity at the cost of increased logical/programming complexity).

Computers have different devices operating at different speeds. As such, there are often multiple devices competing for the bus at the same time. To allow transactions to occur in parallel instead of “taking a ticket”, the system needs to be able to hold data when it becomes available but the bus is busy, until the bus gets freed. It holds that data in a buffer.

I hope that was clear enough. If not, feel free to ask for clarification on anything you didn’t understand.

  • 2
    Buffering in the electronic sense also means interfacing one device with others - for example, allowing the pins of a CPU to be connected to a data/address bus (through a buffer circuit/chip) with multiple devices (RAM, ROM, I/O etc.) connected to it. Such buffers may allow one device to pass signals to many others, invert the logic of the signals to match system requirements or allow the host device to be disconnected from the bus when necessary (tri-state buffers). In this sense the buffers do not actually 'hold' any data for a time period. – Linker3000 Mar 15 '11 at 22:10
  • Right. IIRC (it's been decades) the name for a circuit that holds data is a "register" — and yes, CPU registers take their name from this. – geekosaur Mar 15 '11 at 22:45

These terms can be used in relation to the motherboard also, for example, my college uses 8085 processors in conjunction with what's called a TomAL motherboard.

With TomAL, the information on the data bus is time-multiplexed - the same bus lines carry either the 8 data bits or the lower 8 address bits (A7-A0) at any given time. Peripheral devices know whether it is data or an address using signals generated by the CPU.

The TomAL board employs three chips for bus buffering - there are two 8-bit DFF's (effectively registers) one which holds the higher 8-bits of an address (A15-A8) and another which holds the data of the address/data bus. There is a third, a so-called tri-state, which also holds the data of the address/data bus, but the data it holds is only valid if it is the lower 8 address bits. Otherwise, this chip outputs a signal equivalent to a "don't care" output.

Bus buffering is simply "holding" the data that was on the bus at any point in time. A "buffer" will hold the value that was last written to it until the write line of that "buffer" is set to 1, at which time the contents of the buffer will be set to whatever data is being fed into it. When the write line is set back to 0, the "buffer" will now hold the new value (that is, output the new value), regardless of what data is being fed into it, until the write line is again toggled to 1.

Hope this helps.


The way I understand address multiplexing:

Since row and column pins for memory matrix addressing are the same for n-bit words. You can create a timing scheme (for instance a R/W pin can be used as a clock signal) where on some intervals of the clock the row pins are accessed and column row are split into another. Thus enabling less pins to be used while still passing in n-bit size words to access any cell in the memory matrix.

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