I'm developing a sort of "cache emulator" and I need to know what is the size of the transfer unit between main memory and L2 cache for a core 2 duo processor. Anyone knows it? Thanks.
"Core 2 Duo" processors are made with the Core microarchitecture design.
According to the Intel documentation (Vol. 1, 2-15, page 49 of the PDF), L2 cache has a 256-bit internal data path, so this would be from L2 cache to L1 and instruction fetch/decode.
A few pages later (Vol. 1, 2-32), the Intel Core 2 Duo E6850 has a 10.6GB/s internal data path when the processor core is at 3GHz with an FSB of 1333MHz.
ibus-transfer-amt/bus-clock = (256 bits / (8 bits / byte)) = 32 bytes/clock bytes-per-sec = (10.6 GB) * (2^30 bytes/GB) = 11,381,663,334 bytes/sec ibus-clk-fq = (bytes-per-sec) / (ibus-transfer-amt/bus-clock) ≈ 355,676,979.19 Hz ≈ 355.7 MHz fsb-divisor = (1333 MHz) / (355.7 MHz) ≈ 3.75
The Intel documentation also lists the FSB for this processor at 1333 MHz and 10.6 GB/s, so you should be able to calculate that similarly.