I have completely re-written my post here as I noticed I was a bit unclear before.

In an older post the user sawdust explained very well that there is an SRAM buffer on the HDD controller which uses an ECC algorithm.

I am not sure if the ECC-checksum from the SRAM-buffer is also written to the disks or if it is only to avoid single-bit errors happening inside the SRAM.

But how about the cache memory? All of todays harddisk drives use a DRAM-cache with 64MB or even 128MB. This is a single DRAM-chip on the PCB of every HDD and all data has to pass through it. Such DRAMs do have single-bit errors from time to time and they also suffer from aging. If the data from the cache-DRAM has a single-bit-error, there seems to be no ECC correction here, am I right?

If the DRAM-Cache caused a single-bit error and then this data would go to the SRAM-Buffer, I assume the ECC-logic would now create a checksum "for the incorrect data from the DRAM", but is unable to recognize this error.

HP seems to offer an additional End-To-End parity check which I found described here: http://h20000.www2.hp.com/bc/docs/support/SupportManual/c01159621/c01159621.pdf Parity would not correct, but only detect and eventually request the same data to be transferred again. A permanent DRAM error would lead to endless re-requests of the data-transfer. Wouldn't it be much safer to have the DRAM-cache with ECC as well?

Regards, Tommy

  • Would help a lot to reference to the original question with a link, so we know what you're talking about – Journeyman Geek Aug 26 '13 at 10:24
  • Here is the link to the older post: superuser.com/questions/350582/… – Tommy Volt Aug 26 '13 at 10:46
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    The ECC I was writing about is only for the disk sector. The ECC is computed using a Hamming code, and written with the sector data to detect and correct media errors. The sector read operation retrieves the sector data with ECC. The ECC is then used to detect & correct up to 11 bits in one burst error. ECC is not a checksum. – sawdust Aug 26 '13 at 19:58
  • Ok, so that means the DRAM-cache itself is a potential risk as DRAMs do have single-bit errors from time to time, especially in systems with high utilization. And when there is a wrong bit in the cache, then this incorrect data goes to the sector-buffer where a hamming-code is generated "for the wrong data" and then written to the sector. Sounds critical to me. – Tommy Volt Aug 27 '13 at 8:13

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