I'm looking for some table or something similar that could help me to calculate efficiency of assembly code.

As I know bit shifting takes 1 CPU clock, but I really looking how much takes addition (subtraction should take the same), multiplication and how to presumably calculate division time if I know values that are dividing.

I really need info about integer values, but float execution times are welcome too.


In general, each of these operations takes a single clock cycle as well to execute if the arguments are in registers at the various stages of the pipeline.

What do you mean by latency? How many cycles an operation spends in the ALU?

You might find this table useful: http://www.agner.org/optimize/instruction_tables.pdf

Since modern processors are super scalar and can execute out of order, you can often get total instructions per cycle that exceed 1. The arguments for the macro command are the most important, but the operation also matters since divides take longer than XOR (<1 cycle latency).

Many x86 instructions can take multiple cycles to complete some stages if they are complex (REP commands or worse MWAIT for example).

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    Integer multiply is at least 3c latency on all recent x86 CPUs (and higher on some older CPUs). On many CPUs it's fully pipelined, so throughput is 1 per clock, but you can only achieve that if you have three independent multiplies in flight. (FP multiply on Haswell is 5c latency, 0.5c throughput, so you need 10 in flight to saturate throughput). Division (div and idiv) is even worse: it's microcoded, and much higher latency than add or shr, and not even fully pipelined on any CPU. All of this is straight from Agner Fog's instruction tables, so it's a good thing you linked that. – Peter Cordes Jul 6 '17 at 17:41

Calculating the efficiency of assembly code is not the best way to go in these days of Out of Order Execution Super Scalar pipelines. It'll vary by processor type. It'll vary on instructions both before and after (you can add extra code and have it run faster sometimes!). Some operations (division notably) can have a range of execution times even on older more predictable chips. Actually timing of lots of iterations is the only way to go.

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  • I know that, but I need that not in real project but in one kind a fun programming project. – ST3 Sep 10 '13 at 19:00
  • Whether you need it for real or for fun doesn't change the answer for this processor line. Have you considered switching to a more deterministic processor, such as a Propeller chip, instead? – Brian Knoblauch Sep 10 '13 at 20:22
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    Even with a scalar, in-order implementation branch mispredictions and cache misses can cause variation in run time. – Paul A. Clayton Sep 11 '13 at 11:21
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    For purely CPU-bound stuff (no cache misses, no branch mispredicts), CPU behaviour is understood in enough detail that static analysis can often predict almost exactly how many cycles per iteration a loop will take on a specific CPU (e.g. Intel Haswell). e.g. see this SO answer where looking at the compiler-generated asm let me explain why the branchy version ran almost exactly 1.5x faster than the CMOV version on the OP's Sandybridge CPU, but much closer on my Skylake. – Peter Cordes Jul 6 '17 at 18:05
  • If you're writing asm by hand for performance reasons, then it is actually useful to look for latency and throughput bottlenecks on Intel and AMD CPUs. It's hard, though, and sometimes what's optimal for AMD isn't what's optimal for Intel. – Peter Cordes Jul 6 '17 at 18:08

You can find information on intel cpu at intel software developer manuals. For instance the latency is 1 cycle for an integer addition and 3 cycles for an integer multiplication.

I don't know about multiplication, but I expect addition to always take one cycle.

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  • One cycle, except when it's "free" (in parallel when pipelines line up correctly) or takes longer due to a cache miss. :-) – Brian Knoblauch Sep 24 '13 at 18:18
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    Currently (2018) this information is available in Appendix C named "Instruction Latency and Throughput" of document 248966 "Intel® 64 and IA-32 Architectures Optimization Reference Manual" also available on the page linked in the answer – stefanct Feb 7 '18 at 13:04

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