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On older chip-sets it was not possible to have a dedicated graphics card in the PEG slot and have the Integrated Graphics Device (IGD) enabled at the same time.

After looking online I found this was because they "Shared the same bus lanes" so it was either one or the other and the BIOS would disable the IGD if it detected a card in the PEG slot.

I was just wondering why PCIe devices can't share the same lanes. It is my understanding that with the old PCI standard all devices shared the same lanes so why is this not possible with PCIe?

I know PCIe is serial and creates point-to-point connections between the Switch and 'End Devices' but I don't understand why if the IGD and Dedicated card share the same lanes why they can't work together?

What part of the PCIe design prevents this?

Thanks.

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I was just wondering why PCIe devices can't share the same lanes.

PCIe uses a point-to-point topology, so each lane expects one device on each end. If it wasn't, it'd be something like the original PCI - one issue with plain PCI is that when one device is talking on the bus, others have to wait.

  • Thanks for the answer. I was sort of wondering why the lanes that are used for either the PEG card or the IGD could not be used in some sort of older PCI mechanism where they share same lanes even though they are PCIe devices. Is it just a design requirement with PCIe that each lane can only have one device at the end? – RJSmith92 Apr 19 '14 at 19:57
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    @RJSmith92 - I wouldn't call it a design requirement it simply was a design decision. – Ramhound Apr 19 '14 at 20:20
  • @Ramhound Ye, I could have phrased it better. Thanks for the help. – RJSmith92 Apr 19 '14 at 20:24
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    @RJSmith92 - I was going to make an example to your typical "highway" where a car can't "literally" share a lane with another car. There is always a car in front of you and behind you but two cars can't have equal weight. PCIex16 is 16 lanes but a single device can only use it, think that more of say a shipping "company" fleet all going to the same location. So each PCIex4, PCIex8, PCIex16 would be a single highway for each "shipping" company. – Ramhound Apr 19 '14 at 20:39
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    @Ramhound Thanks, my point was why when using PCIe you could not have 2 devices on the same lanes (like PCI did) and each device only responds when it's addressed and the devices share the bandwidth. Like you said it will be part of the PCIe design that this is not possible. – RJSmith92 Apr 19 '14 at 20:55
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This is the case for electrical reasons. The speed of PCI is limited by the time required for the voltage on the bus wires to stabilize on every clock cycle. The problem is that every time a bus wire is driven high or low, that transition must propagate to all other devices on the bus, and this takes quite a while as the transition literally bounces around for quite some time, reflecting off of every 'impedance discontinuity' anywhere along the trace. This includes the low impedance pin driving the bus wire to Vcc or GND, the high impedance pins of every other connected device, the pins of any unpopulated PCI connectors, etc. This takes quite a few nanoseconds to calm down, and as a result places a hard upper bound on how fast the interface can run.

PCI express is designed to run much faster, and part of that required moving away from a shared parallel bus to dedicated point to point links built with proper high frequency design in mind. That means controlled-impedance transmission line with a single impedance-matched transmitter at one end and a single impedance-matched receiver at the other end along with properly designed controlled-impedance connectors to minimize reflections. Coupled with embedded clocking to eliminate issues with time delay differences between different 'lanes', and the resulting interface can provide orders of magnitude more bandwidth. For example, 32 bit PCI running at 66 MHz provides 2.128 Gbps, which is about the same as the 2 Gbps provided by a single lane of PCIe gen 1. These days, 16 lanes of PCIe gen 4 provides 256 Gbps, a figure only possible due to the modern extremely high performance serial links.

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