Quick question, I was reading the OSDev Wiki page regarding PCI and it says the following -

Base address Registers (or BARs) can be used to hold memory addresses used by the device, or offsets for port addresses. Typically, memory address BARs need to be located in physical ram while I/O space BARs can reside at any memory address (even beyond physical memory).`

I don't get where it says memory address BARs need to be located in physical ram. The whole point of MMIO is that it gets assigned a memory address so that it will be routed to the device and not into physical RAM. What does it mean by it needs to be located in physical RAM?

Wouldn't it just be an address between the 3GB - 4GB address space, regardless of how much physical RAM is installed?

Is this an error on the OSDev site or have I misunderstood?

link - About halfway down, under the heading Base Address Registers

  • @Hennes, link added.
    – RJSmith92
    Apr 27, 2014 at 20:04
  • I just re-read this part: "Typically, memory address BARs need to be located in physical ram while I/O space BARs can reside at any memory address (even beyond physical memory)".
    – Hennes
    Apr 27, 2014 at 20:17
  • @Hennes I'm not sure what you mean? memory address BARs have nothing to do with physical RAM do they?
    – RJSmith92
    Apr 27, 2014 at 20:24

2 Answers 2


I believe there is some confusion here, as there is a difference between I/O and non-I/O devices.
From wikipedia Memory-mapped I/O (MMIO) :

Memory-mapped I/O uses the same address bus to address both memory and I/O devices – the memory and registers of the I/O devices are mapped to (associated with) address values. So when an address is accessed by the CPU, it may refer to a portion of physical RAM, but it can also refer to memory of the I/O device. Thus, the CPU instructions used to access the memory can also be used for accessing devices. Each I/O device monitors the CPU's address bus and responds to any CPU access of an address assigned to that device, connecting the data bus to the desired device's hardware register. To accommodate the I/O devices, areas of the addresses used by the CPU must be reserved for I/O and must not be available for normal physical memory.

From your article :

Base address Registers (or BARs) can be used to hold memory addresses used by the device, or offsets for port addresses. Typically, memory address BARs need to be located in physical ram while I/O space BARs can reside at any memory address (even beyond physical memory).


The Type field of the Memory Space BAR Layout specifies the size of the base register and where in memory it can be mapped. If it has a value of 0x00 then the base register is 32-bits wide and can be mapped anywhere in the 32-bit Memory Space. A value of 0x02 means the base register is 64-bits wide and can be mapped anywhere in the 64-bit Memory Space (A 64-bit base address register consumes 2 of the base address registers available).

Thus there is no conflict between the two, as it all depends on the device. If the device intercepts the memory reference on the bus, then the address is virtual. If it doesn't, then it's real physical address that is used to communicate with the device (for example NVRAM).

However, in all cases, real physical address is used for I/O devices, since computer instructions that refer to it can only use real addresses. This memory may be wasted if the device intercepts references to it. To avoid such waste, the operating system will usually allocate it beyond the real physical memory (this will cause no errors of bad memory access, since the device will intercept all references).

This is the reason for the well-known problem of 32-bit Windows computers not seemingly being able to use the entire 4 GB of memory. The reason was that Windows, being 32-bit, allocated device memory using real addresses, which then became unavailable for both the cases: whether the addressed memory was really used, or unused because intercepted by the device.

Another useful wikipedia article is : PCI configuration space.

  • Thanks for the answer but I'm still not understanding it. For example if we had a 32 bit system with 2GB memory and a PCI device required 128MB wouldn't the BIOS / OS assign it in a memory range between the 3GB and 4GB address space range. What has this got to with 'need to be located in physical RAM'?
    – RJSmith92
    Apr 29, 2014 at 20:17
  • It doesn't have to be located in physical RAM, and for I/O devices it is not usually located in RAM. It just uses physical RAM addresses, addresses that then cannot be used for anything else even if there is real RAM in these addresses. In your example, if the device intercepted the address, then yes, the OS had better use a non-existent address or this would eat up real RAM.
    – harrymc
    Apr 29, 2014 at 21:15
  • For a too-simple example: a computer having 2GB is allocating the hard disk buffer at 3GB. The OS uses a hardware instruction to write or read from address 3GB. The disk controller intercepts this and converts it to read or write on the hard disk. The hardware instruction in a 32-bit instruction can only refer to addresses in the range of 0 to 4GB, so the allocated driver memory needs to be mapped to that range to be addressable. The address doesn't have to exist to be addressable.
    – harrymc
    Apr 29, 2014 at 21:15
  • I understand that but my point is why it says 'located in physical RAM'? what has physical RAM got to do with this? I know it uses physical RAM address space (usually between 3GB and 4GB). Do you think that's what it means?
    – RJSmith92
    Apr 29, 2014 at 23:01
  • Yes, that's it. The address is of physical RAM. I think that your problem is with the word "located", which I agree is somewhat inappropriate here. "Mapped" might be better. The address is just a number that is put on the bus and that, unless intercepted by some device, is handled by default by the memory controller (itself just another device). In the chip itself of course the implementation is heavily optimized and not as simple as that, but globally that's the mechanism that is used and the way it's explained to laymen.
    – harrymc
    Apr 30, 2014 at 5:33

The address bus width determines the size of the physical address space. But not all the values within this space are claimed by memory controllers. Some are claimed by other types of devices. The BAR register implicitly encoded the address range size requested by the PCIe device/function. But where the base of this range is must be properly configured. Then the device can automatically claim the request with the address falling into its range. This arrangement is all configurable during the system initialization/boot phase.

An useful illustration:

enter image description here

From the perspective of a software engineer, I think the most important thing to know is not how all these plumbing is implemented for a computing architecture. But by what means the hardware resource is exposed to software. For x86 architecture, it can be memory address, or IO address.

  • This post dates from 2014. It's unlikely that the poster is still watching it.
    – harrymc
    Aug 28, 2021 at 10:02
  • Hope it can help people besides the poster. Aug 28, 2021 at 13:39
  • how do you mmap on I/O space? Is there a difference wrt to memory mapping to ram?
    – user217354
    Jun 16, 2022 at 13:55

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