So the manufacturing processes for CPUs goes down every second generation (for Intel), but I couldn't get the math right. Let's say we have a CPU with a size of 10mm*10mm, that makes a die area of 100mm^2. And let's shrink the manufacturing process let's say from 100nm to 90nm, so a 10% reduction. Would the same chip with the new process be of dimension 9mm*9mm? That would mean the reduction is linear in length, and therefore quadratic in the die size, because the new die size is 0.9^2 * 100mm^2.

The reason I'm asking is because I was doing some rough calculations based on the Sandy / Ivy Bridge Shrink and die sizes, and couldn't get a good answer. Sandy Bridge was 32nm, Ivy was 22nm, that's a factor of ~1.45. According to Wikipedia the die sizes of the two most comparable models (4 cores, same L3 cache) are 216mm^2 and 160mm^2. That makes a factor of 1.35 while it should be over 2 because 1.45^2=2.10. Or does the production process affect the die size linear, not the width/length? But then: why? And the other shrinks don't really add up either. Or is the real problem the architectural changes besides the production process? i.e. more transistors. I'm confused.

  • Ivy is actually larger than Sandy Bridge if you correct for the reduction in process. 160mm^2 * 1.45 = 232mm^2 > 216mm^2 – Dan D. May 8 '14 at 7:47
  • Well that's exactly the question. Does the process go linear in die size, like you said? Or quadratic? – Basti May 8 '14 at 8:09

As you allude to toward the end of your question, you need to add a third factor: the transistor count.

Each transistor becomes smaller, but since the number of transistors also changes, the total die area does not change in direct proportion to the transistor size.

For a perhaps extreme example, consider an older CPU like perhaps the Intel 80486. I can't immediately seem to find exact, comparable numbers, but the 486 had about a million transistors and what looks to have been a 600 nm manufacturing process. The Ivy Bridge uses a 22 nm process and crams around 1.4 billion transistors onto dies varying around 150 mm^2 in size. With the 80486 level of technology we'd then be looking at a die on the order of 1,000 times the size of that of the Ivy Bridge, or 0.15 m^2.

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    There are also transistors that do not scale such as those driving I/O pins (probably not significant). There are also areas of a chip whose size is wire limited; wire width has not shrunk as fast. Complicating such an evaluation, the 32nm to 22nm change also had a transition to FinFET. The Electrical Engineering SE could probably provide a more detailed answer. (I am not an EE, have not played one on television and did not stay at a Holiday Inn Express last night.☺) – Paul A. Clayton May 8 '14 at 15:34

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