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In L1, L2 cache and DRAM, is sequential access faster than random access because of the possibility to establish read-ahead? I know in HDDs this is of-course faster in orders of magnitude.

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YES, some the same but not the same exactaly.

According to the manuel for the processor :-)
http://www.intel.com/content/dam/doc/manual/64-ia-32-architectures-optimization-manual.pdf

There is specific hardware prefetching, and a programmer can tell it to prefetch, plus there are ways that it works in chunk size of data that an aware programmer could gain advantages from. Also the same hardware or software methods done slightly incorrectally might cause the prefetch to be tossed, over and over again, plus things like this varied for different processors.

Moving data into the higher levels assuming it will be needed (like read-ahead), and the data being there because it was within the chunk size that it moves into those levels (being sequential could help).
The processor knowing what instruction set it has quoed up in there, or the list of things it is going to do, it gets that data ready.

2.1.5.4 Data Prefetching Data can be speculatively loaded to the L1 DCache using software prefetching, hard- ware prefetching, or any combination of the two. . . .

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Streamer: This prefetcher monitors read requests from the L1 cache for ascending and descending sequences of addresses. Monitored read requests include L1 DCache requests initiated by load and store operations and by the hardware prefetchers, and L1 ICache requests for code fetch. When a forward or backward stream of requests is detected, the anticipated cache lines are prefetched. Prefetched cache lines must be in the same 4K page. . . .

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Wide Dynamic Execution  
Smart Memory Access - prefetches data  
Branch Prediction Unit  
Instruction Fetch Unit  
Instruction PreDecode  

The list goes on and on with many features that are thinking ahead.

Start at Page 60 of the linked document.

https://stackoverflow.com/questions/1922249/c-cache-aware-programming More PDFs are linked to at Stack Overflow, and I am sure way more info there about it.

The data on this and the technique is to long to post here, and all the "how that works in reality" from the programmers would be to long also. Not only that I only barely understand it. After reading that (and programmer info) it is no wonder why one piece of software doing almost the same thing, can be 50 times faster than another, things could be meticulously done and tested and retested, to have the ultimate optimisation , or they could miss a few things and be normal.

& NO, ram is all fully random access, there are only tiny ammounts of latency, it is "Ram" that a hard drive uses to do read-ahead actions, and burst transfers at many times faster than in can be read from the platters. Sequentiality is hugely important on hard drives because head movement takes time and is not pulling data off the platter then. After the head arrives at the location, it has to wait till the data comes up in the rotation.
With Hard drive read ahead it might pull data on the same rotation saving many miliseconds of time.

It might be a huge stretch in imagination :-) to assume there is anything similar about the 2.

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    DRAM is not perfectly random access, a read from an open DRAM page/row will be faster than when the bank has no page/row open (since a row ACTIVATE command must be processed by the bank) much less when another page/row is open in the same bank of the DRAM (since that bank needs to process a PRECHARGE command before the row ACTIVATE command can open a new page). Nov 16 '14 at 1:10

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