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I read in the Foundation of Computer Science(by Behrouz A. Forouzan) textbook that a Von Neumann model's program must execute sequentially and the modern computer executes code in the order that's most efficient. But it did not say the Von Neumann sequential approach is the most efficient.
So does the modern computer execute code this way?
Architecturally, i.e., with respect to what software sees, modern processors use the serial von Neumann model. However, most high-performance processors use out-of-order execution, which allows operations to be executed in a non-serial manner but their effects are committed in program order.
(Some earlier, in-order processors had imprecise exceptions caused by operations beginning execution in-order but the results being committed as they became available. This means that a shorter latency operation, such as an integer addition, coming after a longer latency operation, such as a floating point multiplication, can write its result to a register before the longer latency operation completes. If an interrupt or exception occurred before the longer latency operation completed, the program state would be inconsistent.)
A dataflow architecture does not execute programs serially, but scaling the dependency handling hardware is problematic (even modern high-performance out-of-order processors have execution windows from which candidate operations are scheduled of less than 100 operations) and ensuring correctness (particularly for software, where formal methods are less common) is also difficult. To get a feel for the design, each operation is treated like a separate thread that can begin execution as soon as its source operands are available and can commit its result as soon as the operation completes (allowing operations waiting for only that result to begin execution). At the machine language level, this could be viewed as the ultimate multithreaded spaghetti code.
Processors that use out-of-order execution are like dataflow architectures in operation but with limited execution windows and guaranteed in-order visibility of results within the same thread of execution. (Weaker memory consistency models will allow results to become visible to other processors in an order that is not strictly sequential.)
The key distinction between the major Von Neumann and Harvard architectures is that with Harvard, Data and Program memories are separated. Todays PCs are using a shared memory for that, although certain memory regions may be marked as non-executable, the same data bus is used for them. So from that point of view, PC architectures are definitely Von Neumann.
Modern processors for desktop PCs will however reorder instructions based on efficiency, but this is, from what I learned, not the key point for a Von Neumann architecture.
Von Neumann model's program must execute sequentially
modern computer execute code in the order that's most efficient.
Modern general purpose CPUs still consume a single instruction stream (per logical CPU anyway) and while Intel/AMD CPUs do internally re-order operations (particularly slow memory operations) to enhance performance, it does this only when it won't affect the results of the instruction stream.
So modern CPUs still work sequentially - I guess the official "workaround" to this has been to introduce logical CPUs - Intel's hyperthreading technology allowed many operations to overlap and occur at once, and the interface it presented to the instruction stream was a second logical CPU.
But it did not say the Von Neumann sequential approach IS the most efficient.
Well, with computers becoming media devices, if a CPU has to crunch on a large amount of data, but with simple operations not requiring a lot of decision making, the pure sequential approach isn't efficient. So SIMD instructions have been introduced that allow the CPU to load a bunch of values and fire an operation at all of them in one cycle. And of course, GPUs work differently, with many, many "cores" that do simple math operations on huge amounts of data in paralell.
From wikipedia:
The design of a Von Neumann architecture is simpler than the more modern Harvard architecture which is also a stored-program system but has one dedicated set of address and data buses for reading data from and writing data to memory, and another set of address and data buses for fetching instructions.
Modern Computers have not moved away from the Von Neumann bottle neck. Even if we were to use thousands of CPU's in a super parallel array, they would still each incorporate the principle of an ALU, so they are still largely based upon the same concepts. By creating multiple parallel bottlenecks, we alleviate the problem, but the individual building blocks are fundamentally the same.
