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If I have a CPU with two cores, each core has it's own L1 cache, is it possible that Core1 and Core2 caches a same part of memory at the same time?
If it is possible, what the value of the main memory will be if both Core1 and Core2 have edited their value in cache?

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If I have a CPU with two cores, each core has it's own L1 cache, is it possible that Core1 and Core2 caches a same part of memory at the same time?

Yes. Performance would be terrible if this wasn't the case. Consider two threads running the same code. You want that code in both L1 caches.

If it is possible, what the value of the main memory will be if both Core1 and Core2 has edited their value in cache?

The old value will be in main memory, which won't matter since neither CPU will read it. Before ejecting a modified value from cache, it must be written to memory. Typically some variant of the MESI protocol is used. In the traditional implementation of MESI, if a value is modified in one cache, it cannot be present at all in any other cache at that same level.

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Yes, this (having two caches cache the same memory region) can happen, actually it is a problem that occurs a lot in practice. There are various solutions, for example:

  • the two caches can communicate to make sure they don't disagree
  • you can have some sort of supervisor which monitors all caches and updates them accordingly
  • each processor monitors the memory areas that it has cached, and when it detects a write, it throws out its (now invalid) cache

The problem is called cache coherency. The Wikipedia article on the topic has a nice overview of the problem and possible solutions.

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To answer the question in your title, it depends on what the caching protocol is. If it is write-back, the cache will only be flushed back to main memory when the cache controller has no choice but to put a new cache block in already occupied space. The block that previously occupied the space is removed and its value is written back to the main memory.

The other protocol is write-through. In that case, anytime the cache block is written on level n, the corresponding block on level (n+1) is updated. (It is similar in concept to filling our a form with carbon paper underneath; whatever you write on top is copied on the sheet below.) This is slower because it obviously involves more writing operations, but the values between caches are more consistent. In the write-back scheme, only the highest level cache would have the most up-to-date value for a particular memory block.

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    I wonder what percentage of readers here have ever used carbon paper. :) – Barmar Jan 30 '15 at 18:41

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