ORIGINAL QUESTION: (you can read this mess of a question, but I suggest jumping to the re-written question)

I see that there are a lot of places mentioning 16 EB RAM limitation... However, isn't a modern register 64 bit? and if so, 2^64 should point to the number of registers possible and since they are each 8 bytes, the actual limit should be 128 EB ((2^64)*8 bytes). Example: 32 bits go to one decoder of 32X(2^32) and the other 32 bits go to the other 32X(2^32) decoder in order to switch on the right wires in each decoder and therefore access a specific register of the (2^32)^2 registers available, each one having 64 bits of data (for the 64 bit bus to be saved).

Clearly I am either missing something or there's an odd chance that I am right and 16 EB is not really the limit...


This was written a long time ago, when I was teaching myself about RAM, I've stumbled across multiple sources that contradicted (at least in my mind, but I can't remember exactly why I got confused enough to write a question about it) and must have gotten confused.

I would like to re-clarify my original question rather than deleting so that it's more useful to future readers (but I don't need an answer, I've taught myself about this a few years ago and even got a Computer Science degree since then).

THE QUESTION: (written in a way that's more useful to other people)

When I was asking this question, I used the term "register" very loosely to refer to a memory location and assuming that RAM was word-addressable (hence the use of 8 bytes for a 64 bit architecture). If RAM was word-addressable, each memory location would hold 8 bytes and therefore 16E * 8 bytes = 128EB.

As most modern computers use byte-addressing, the actual size of each memory location would be 1 byte (8 bits) and therefore 16E * 1 byte = 16EB.


Having byte-addressable RAM makes it easier to manage so that the difference between 32 bit and 64 bit isn't as big, but a call to RAM would still get the entire 64 bit word (by ignoring the last 3 bits of the address for the retrieval part, then if only 1 byte is needed, the other 7 bytes can be ignored).

Another useful note: in 64 bit addressing, usually only 40-52 bits are used, this leaves a sufficient amount of maximum RAM (between 1TB and 4PB).


On a 32-bit architecture, pointers contain 32 (usable) bits, and can address 2^32 (=4294967296) different addresses. Each address points to a byte, so your address space is 4294967296 bytes, or 4 GiB.

On a 64-bit architecture, the same argument holds: You can address 2^64 different addresses, and each address points to a byte, so your address space is 2^64 bytes in size, which is exactly 16 EiB.

However, please note that on (current) x86_64, pointers only have 48 usable address bits to save some silicon. Trying to access invalid addresses will result in a CPU exception, since it doesn't implement the other bits. The architecture will be extended when the additional memory becomes practical, though.

  • so the register is 8 bit... if so, how is the 64 bit data bus saved? in 8 different registers? wouldn't that require 8 cycles? – user1683642 Aug 7 '15 at 16:00
  • A 64-bit register contains 64 bits, which is 8 bytes. – Sebastian R. Aug 7 '15 at 16:13
  • @user1683642 - Where did you get registers are 8-bits from. I see no mention of that in this answer. – Ramhound Aug 7 '15 at 16:13
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    I think you have read some documentation on how old DRAM was connected 20 years ago and got a lot of it backwards. Modern RAM works differently. But this is not the place to discuss this any further. – Sebastian R. Aug 7 '15 at 16:20
  • Ok, thanks... I'll open a new thread for that after reading some newer sources...(if I still don't understand) seems weird that they would change it because the old one would actually make the limit higher (128 EB) – user1683642 Aug 7 '15 at 16:21

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