Questions tagged [computer-architecture]

Computer architecture refers to various aspects of computer system designs which can affect compatibility, performance, and interfacing. Some issues related to computer architecture can be processor word size, memory bus size, or protocol implementation.

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DDR4-2933 data transfer rate

DDR4-2933 functionates at 2933 MHz How do I find peak data transfert rate in GB/s from there ? Is it vendor/capacity dependent ? Is there a universal conversion approach ? It should be something ...
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GPU cores vs. CPU cores

A (say NVidia) GPU is made of streaming multiprocessors consisting of arrays of streaming processors or CUDA core. There are 5120 CUDA cores on V100. A general purpose (say Intel) CPU has "only" up to ...
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Computer Won't power on unless clear CMOS every time by removing MB battery and putting it back

hi all I am new to this forum hope everyone is fine I am having a strange problem on my computer just like my topic says and my motherboard is Gigabyte h170m-d3h. my computer worked fine for about a ...
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If firmware is a CS concept, how is it defined?

I have a problem understanding the term firmware (as a type of software); If it is a CS concept, it might be good to ask about it here to get a formal definition and a correction for my mistake, as a ...
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Why do we need PHY Interface between DDR Controller and DRAM Memory?

Is it required to have PHY in all the systems, if not what happens ? if PHY is removed can we still pull the data from DRAM memory using the DDR controller ? if yes, then why do we need to have PHY ...
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How can I fix the error “boot! And select proper boot device”?

I tried to fix that. Pressed ctrl+alt+Del and it shows the motherboard settings. I don't know what should I do?
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Does UEFI run on top of BIOS?

This page: https://wiki.osdev.org/UEFI and few others which are rather creditable mention that UEFI is kind of an application which run on BIOS (legacy BIOS) and not a firmware If I got it right. Some ...
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Why MLC ssd has lower TBW than TLC?

I have ssd's. Crucial mx100 250GB: MLC, TBW 72. Crucial mx200 250GB: MLC, TBW 80. Adata sx8200Pro 250gb: TLC, TBW 160. From many sources I learnt that MLC should last ~ 6-10 times more writes than ...
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How to install armhf packages on an x86 host

I am trying to cross-compile some libraries for an ARMv7, and one of the needed prerequisites is python3-dev:armhf. I am starting with a fresh debian docker-container (docker pull debian) so this ...
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How does multicore CPU thread synchronisation work at the hardware level?

I'm trying to understand how multicore CPU's implement thread synchronisation at the hardware level. From my research so far I've found that the process involves using a location in memory to act as ...
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Instruction set and pseudo-command

I use 'objdump' on linux in a variety of binaries and it returns their assembly. The commands that I receive is 'real' commands or pseudo-command? I have read that there are some commands which are a ...
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HDD : Data is written on HDD sequentially or round robin fashion?

Say I need to create and save the file data on HDD. HDD is nothing but a stack of multiple spinning disks. My understanding is file data is divided in to number of memory blocks which can be saved to ...
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What are the Memory Locations in Random Access Memory? [closed]

What is the meaning of memory locations in Ram. I really do not understand the definition of the word memory location in RAM. Tell me which English dictionary in google you used to find the meaning of ...
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Creating an overflow for a 8 bit binary [closed]

Hi everyone I am new to this site, apologies if this is in the wrong section. I have made a 8 bit diagram to represent 2's compliment however when the binary reaches the maximum of 255 I would like to ...
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DDRAM Rack and channels

I have a question regarding the DDRAM architecture: I was reading a scientific paper regarding a new processor that reduces power consumption while keeping a very high level of performances, and as ...
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Can one use 4-bit, 8-bit, 16-bit, or 32-bit sized pointers on a 64-bit machine?

I just did a rough calculation around the max size of an unsigned 64-bit integer, which is: 18,446,744,073,709,551,615 q5 q4 t b m t h Looking at AWS's hardware specifications on their ...
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calculate avg time to read bytes on a disk

Question gives me following parameters: track seek time = 10ms (milli-second). The rotation speed of disk= 9000 revs per minute Sectors on each track = 600 Each sector can store 512 bytes of data....
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How can 4 GB be equal to 32 bits memory address?

Forgive me for being naive to ask this question. How can 4 GB be equal to 32 bits memory address? If i am not mistaken, 4GB * 1024 * 1024 * 1024 = 4,294,697,296 bytes of memory cells. So, why we don'...
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I want to know the real speed of SDRAM [closed]

I looked a lot of sources, but nowhere information about speed and access latency of static RAM, unlike other types of memory like SDRAM and other.
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Inserting CMOS battery upside down

What happens when CMOS battery is inserted upside down? What is it capable of damaging? Power supply, entire motherboard or specific ICs.
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Graphic card lights up but newly built PC won't turn on

This is my first time of and I assembled my new PC and it is not starting for some reason. Though, strange my GPU is lights up but nothing else. I've checked the compatibility of each devices and they'...
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Do any chip architectures feature instruction primitives for complex numbers?

Just curious if there are any computer chips with builtin operations for manipulating Complex numbers, or if one must roll their own using Real ops for now.
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What is “Out-of-band Remote Access”?

DMIDECODE: Handle 0x001E, DMI type 30, 6 bytes Out-of-band Remote Access Manufacturer Name: Intel Inbound Connection: Disabled Outbound Connection: Enabled LSHW: *-remoteaccess UNCLAIMED ...
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pthread_attr_setaffinity_np and logical core

I am a bit confused about CPU logical cores and physical cores and scheduler affinity. Let's assume there is a 4 physical core CPU where each core supports 2 hyperthreads. Henceforth, according to /...
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Unattend.xml file - Processor Architecture

I'm trying to install a Windows 10 image using Windows Deployment Services. In the unattend.xml file, processor architecture is defined as below: <component name="Microsoft-Windows-Setup" ...
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What is a processor core at the hardware level?

I have been studying how processors work and its different parts including the ALU, registers, control unit, and a question came to my mind concerning multi-core processors. What are the cores made of?...
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BUSYBOX: How do I check if I have a 32 or a 64 architecture?

I am on a Busybox and uname –a results: Linux 3.14.28-1.12 #1 SMP Thu Jun 15 08:53:06 CEST 2017 armv7l GNU/Linux. Is this a 32 bit architecture or how can I check it?
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X86 Address Space Controller?

I understand that on x86, certain ranges of physical memory addresses are mapped to the BIOS, others to RAM and yet others to I/O devices. I would like to know which hardware component is ...
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Is it correct to say that main memory (RAM) is a part of CPU?

I recently had an argue with my English teacher, because of text given to us for translation. It states: The pieces of equipment making up the computer system are known as hardware. The most ...
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Intel Phi Coprocessing for Desktop PC

My question is, if I want really take advantage of all the novel advances for data-spec'd computing that are available right now, i.e.: Xeon Phi (and upcoming Knights Mill), 3dx point ssds, ect, Can ...
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Intermediate code by virtual machines

I was reading about instruction set and I came across following line from WIKI Some virtual machines that support bytecode as their ISA such as Smalltalk, the Java virtual machine, and Microsoft'...
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Do we have ROM in Von Neuman Architecture? [closed]

According to Von Neumann architecture ,we have a single Program and Data Memory which is called RAM ,and ROM is a program Memory in case of harvard architecture so do we have ROM in Von Neumann ...
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How is the word size often same as pointer size?

A pointer stores a memory address , so its size is the size of a memory address which depends on no of memory locations . On the other hand , Word size is the largest unit ,that an instruction can ...
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What is the difference in instruction completion rate, instruction throughput, instructions per clock? [closed]

From what I understand: ICR (Instruction Completion Rate): Is (# of instructions / time) Instruction Throughput: Is usually an average of the number of instructions completed each clock cycle. IPC (...
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Is there any existing CPU implementation which uses one's complement?

Programming languages like Ada or VHDL define an integer datatype as -2^31+1 to 2^31-1. This rule goes back to CPUs with an one's complement ALU. It allows the program to run on one's and two's ...
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What is a RAM Bank? How is it defined?

I've been looking around, and I can't seem to get a solid answer on what a Memory Bank is in RAM. Some say that it's something like a channel, others like a DIMM slot, others say it's just an ...
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1answer
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why separate floating point registers intel x64 processors

Why are there separate floating point registers xmm0-xmm15 in intel x64 CPUs? I know xmm's are also used for vector operations where some instruction(SSE*) is executed on several numbers in one ...
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Relationship between the size of CPU registers and main memory

I have read this post however I still have a question. I understand that saying 32 bit processor implies registers of size 32 bit long each of which can hold up to 2^32 data. What does it mean saying ...
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Computer needs several attempts to power on? (Much like a bad car)

I've had a look at the available stack exchange forums and i have concluded that this one might be the most relevant for my question, though it does adhere to personal computing. Please inform me if ...
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what is the the reason CPU utilization gets high?

For simplicity, lets consider I have a single core processor. I have 2 task running in parallel. My understanding is the processor will run the tasks in round robin fashion i.e. one at time time. ...
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The use of micro-instruction cache

I learnt recently that Sandy Bridge uses a micro-instruction cache akin to the execution trace cache in Netburst. From what I know, many of the simpler x86 instructions (those translating into 4 micro-...
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estimating copying 1GB file from one USB flash memory to second USB flash memory

Into host USB (image below) there are plugged two flash memories. I would like to estimate minimal time of copying one file 1GB to second flash memory. It is fairly difficult for me, I assume ...
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Is it possible to 'blend' two processors from different computers into one “supercomputer”? [duplicate]

Maybe this is a little bit crazy, and I have the suspicion that it is impossible, however here is the situation. I have an old Xbox which I don't use, and I think it's a shame that all that storage, ...
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What the technical difference between Serviceability, Manageability and Maintainability of a system?

Aren't Serviceability and Maintainability almost serve the same purpose in term of IT architecture so how to they exactly differ?
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operations process in a computer

Is it true that all high-level operations in a computer (say, copying, pasting, web surfing, running apps etc) are all finally converted to micro-operations (say, arithmetic, logical and shift) and ...
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How byte addressing works?

I am new to computer architecture. So correct me if I am wrong. If a memory module consists of 8 memory chips and if each chip stores 4bits per address then by applying an address to the address pin ...
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What does it mean (to decode) in the execution cycle

In a typical instruction cycle, fetching, decoding, executing together form one cycle. My question is about the decoding step: What is the part that gets decoded, is it the instruction's opcode? If so,...
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Is there a difference CPU Clock and Instruction Clock?

I am a bit confused between CPU clock and instruction clock. I brought the following figure from this source as illustration. Does instruction clock imply the time it takes by the cpu clock to execute ...
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CPU clock cycle and instructions interpretation

I am new in computer architecture but I know the main topics since I had it as a course before. My question is in fact little deep and related to CPU clock cycle and how processor interpret ...
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The main difference between Superscalar and Parallelism

In superscalar processing, more than one instruction is executed in parallel at each core, so how would that differ from parallel processing then? Thank you.

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