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Questions tagged [cpu-architecture]

CPU Architecture refers to a collection of parameters about the design of CPU realized by its manufacturer, such as: its bit-ness or data bus width (16, 32, 64 bits) , Instruction Set (RISC, CISC,...), Memory Management, Threading, Virtualization support, etc

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What exactly do we mean when we say 64-bits CPU? [duplicate]

Finding some mixed answers on this topic. It seems like it either means how many wires there are on an address bus (so 64 bits would mean 64 wires so we could address 2^64 bits) or how much data we ...
WaveCave's user avatar
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2 answers
110 views

Instructions per Cycle (IPC) vs Frequency

I'm working on core frequency scaling experiments and I see that with the increase in core frequency (all other stuffs untouched, for example ddr frequency is kept same), I see decrease in IPC values. ...
srccode's user avatar
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Debian multiarch hello:i386 "cannot execute binary file: Exec format error"

I followed the wiki - https://wiki.debian.org/Multiarch/HOWTO $ sudo dpkg --add-architecture i386 $ sudo dpkg --print-architecture arm64 $ sudo dpkg --print-foreign-architectures i386 $ sudo apt ...
HankCa's user avatar
  • 101
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28 views

How do base and turbo frequencies affect core utilization in multi-core CPUs?

I'm trying to understand the relationship between base and turbo frequencies in multi-core CPUs, specifically regarding core utilization. My CPU has a base frequency of 2.1 GHz and a turbo frequency ...
sako's user avatar
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-4 votes
1 answer
72 views

Converting OS opcodes

I cannot boot Windows 3.1 (by the way, I don't actually mean to boot Windows 3.1, it is just as an example, so don't tailor your response for specifically how to boot windows 3.1) directly on my ...
Jimmy Zeng's user avatar
-1 votes
1 answer
197 views

Why do SIMD CPU extensions exist?

As I understand the problem there are problems that can be heavily parallelized, e.g. rendering, video decoding. Since CPUs are not excelling in such tasks GPU were created. They use different ...
TonyDecvA180XN's user avatar
0 votes
1 answer
58 views

Understanding count of logical processing units in Qualcomm SOC

I have Qualcomm RB5 board. Its SOC spec sheet says following: CPU: Kryo 585 CPU, 64-bit, up to 2.84 GHz ISP: Qualcomm Spectra 480 ISP with Dual 14-bit image signal processing GPU Adreno 650 GPU w/ ...
RajS's user avatar
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1 vote
2 answers
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Where are Model-Specific Registers (MSRs) physically located?

Specifically talking about Intel MSRs, where are they physically located in the computer ? Are they inside the CPU just like other general purpose registers? Are they mapped to RAM ? To read/write an ...
Viaceslavus's user avatar
-1 votes
2 answers
208 views

Exception and Interrupt difference

I know a Exception is a software Interrupt however after a Interrupt the program counter always returns to the address before the Interrupt was thrown but after a Exception a program may be terminated ...
Volpina's user avatar
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2 answers
566 views

Difference between Number of CPU cycles of a device and CPU frequency of a device

I am a researcher working upon task offloading among IOT devices. While programming for my work, I have come across two terms that is Number of CPU cycles of a device and CPU frequency of a device. I ...
Zainab's user avatar
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1 answer
774 views

Is the ARM instruction set the same for all ARM processors?

Is the ARM instruction the same on all ARM processors? Or just a subset of it is mandatory and universal? For instance, when Apple was designing the Mac silicon, could they have modified the ...
Caio's user avatar
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0 answers
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What MSR to read to understand why my laptop CPU is sometimes stuck at 800Mhz?

I have a Dell Precision 7550 with an Intel Xeon W-10885M (Comet Lake), and sometimes, on Ubuntu only (not on Windows), my CPU get stuck at 800Mhz when plugged in (no problem on battery). I'm trying to ...
Vincent's user avatar
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34 votes
12 answers
10k views

Why are most of the common processors' bit counts powers of 2?

Most of the processors/CPUs widely used today, have a bit count that is a power of 2 (usually 32 and 64, but also 16, 8, and 4 bits). Even though the meaning of bit count isn't consistent (some say it'...
SamFF's user avatar
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1 answer
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Is the ARM specification just an instruction set, or more?

Is ARM specification just an instruction set, or does it include more than that, for instance hardware implementation details? I guess that the value of ARM Limited as a company (around 30G$) does not ...
PierU's user avatar
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Fix MBR for a 16-bit intel 80386sx cpu [duplicate]

i have an old classic computer running ms-dos 3.30 on computer architecture running a 16-bit cpu (80386sx, not to mistake with 80386DX which is 32-bit), i was playing around and messed up the MBR. I ...
Aqil Mehmood's user avatar
-1 votes
1 answer
98 views

Computer Architecture – Why are they different even if the machine is the same?

I've got a Raspberry Pi 4. If I install NOOBS / Raspbian and run the comand. uname -m I get armv7l as an output. If I install Ubuntu on the very same Pi (same hardware) Running uname -m yields arm64. ...
Some random IT boy's user avatar
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1 answer
186 views

what is the supposed size of address bus 16 bits to address a memory of 8ko?

I don't know how to distinguish between the size of bus address and memory size when I supposed to answer this question in my homework: what is the supposed size of address bus 16 bits to address a ...
Akram BENGHANEM's user avatar
33 votes
3 answers
30k views

What are performance and efficiency cores in Intel's 12th Generation Alder lake CPU Line?

I watched Intel's Architecture Day 2021 released in August 2021 (last month at the time of writing this). After watching Intel's video about their new CPU, I was — quite honestly — a bit confused. I ...
JΛYDΞV's user avatar
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1 vote
0 answers
314 views

Can different active cores of a desktop Intel x86 CPU run at different frequencies at the same time?

According to FAQ for Intel® Turbo Boost Technology, the turbo frequency is the same for all active cores. Intel's 8th and 9th Gen Datasheet, Volume 1 (PDF) also mentions that: All active processor IA ...
Wildcat's user avatar
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2 answers
811 views

Processor with a higher IPC vs Processor with lower IPC but specific instructions

Context: Intel and AMD have long been fierce competitors in the CPU industry. As of late, AMD seems to have managed to make processors with a higher IPC on a single core than Intel (e.g. the Ryzen ...
Prithvi Boinpally's user avatar
-1 votes
1 answer
44 views

What was the need to create different processor architectures? [closed]

I have been studying processors for a while and I found out that there are a lot of processor architectures available. Once we got a working processor architecture, why did we create other ...
Shreemaan Abhishek's user avatar
-5 votes
1 answer
495 views

CPU max utilization limited to 1/N CPU’s for MOST multi-threaded Apps on any Win OS : WHY?

I understand multi-threading and tasking to some extent but know that outside of the OS, most Windows Apps are limited to using only 1/N CPU’s for averaged max. utilization. That is 50% for a dual ...
Tony Stewart EE75's user avatar
1 vote
1 answer
189 views

Why aren't CPU instructions decoded before the program runs?

What is it about the decoding step of the instruction cycle that prevents it from being done ahead of time? The Intel 64 manual says things like "decodes instructions into micro-operations". ...
Matt Kleinsmith's user avatar
0 votes
1 answer
144 views

Calculate upper memory limit of M1 chip [duplicate]

Why the M1 chip memory limit is set to 16GB,it is mentioned here that it is based on 64 bit ARM architecture, shouldn't it share the same memory limit which is 16 Exabytes? According to the linked ...
user10191234's user avatar
0 votes
1 answer
18k views

Will Python be able to run on the new Apple machines running with M1 CPUs? [closed]

I am getting the new Apple MacBook with its ARM processors. I am wondering if Python will be supported on this new line of Macs. If it is not supported yet, then when will it be supported?
neuops's user avatar
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4 answers
12k views

How can I find my computer's address bus width and data bus size?

I have a 64 bit x86 (x86-64) computer. Does that mean my address bus is 64 bit? I am trying to calculate addressability and address space as explained here. I don't really have any clue how to find my ...
notacorn's user avatar
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1 vote
0 answers
23 views

Where are the actual bytes located within DIMM modules in dual or multi-channel mode? [duplicate]

I'm trying to find out how memory is arranged in dual channel mode, i.e. which memory addresses are on which DIMM. What I have currently found out is that there are two modes "ganged" and &...
Maarten Bodewes's user avatar
2 votes
0 answers
178 views

Privilege levels in 64bit Intel architecture [closed]

I'm currently reading this paper and while this is probably a very basic question, I can't find an answer: In the Privilege Level chapter, how does the CPU know in what privilege level it's currently ...
DreamsInHD's user avatar
-2 votes
1 answer
390 views

Do Operating Systems need to know which is the hardware architecture on which they are executing?

Maybe this is a basic theoric question, but I have no idea of the answer and haven't found information of this. Do Operating Systems (imagine Windows or Linux distros) need to know if they are ...
isma's user avatar
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7 votes
9 answers
8k views

Where does the "2" in 2^n come from when computing max memory size? n=n-bit

So I was reading up on address buses and max memory sizes, so my question is, when computing max memory size for any architecture, where does the 2 in 2^n where n is the address bus bit size come from?...
Sam Pan's user avatar
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5 votes
2 answers
21k views

GPU cores vs. CPU cores

A (say NVidia) GPU is made of streaming multiprocessors consisting of arrays of streaming processors or CUDA core. There are 5120 CUDA cores on V100. A general purpose (say Intel) CPU has "only" up to ...
kiriloff's user avatar
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0 answers
154 views

running an existing system based on i686 Centos 6 on a 64 bit architecture

I want to run an old Centos 6 based program (i686) on my Core i5 CPU but it doesn't seem to work although I have enabled virtualization. It's a pretty complex system with lots of software libraries ...
peterbrown's user avatar
3 votes
3 answers
4k views

How the CPU determines whether to put data in L1i or L1d

How does CPU decides what cache to use to store data just retrieved from memory? As far as I know the smallest unit of memory that CPU can access (read or write) is 64 Bytes (x86_64, DDR3/DDR4) which ...
turbocoder's user avatar
0 votes
1 answer
213 views

Does the instruction register have to send its memory address to MAR before accessing memory?

I am studying computer systems and operating systems and I have been confused about when a memory address would be transferred to the memory address register (MAR). When the instruction register (IR) ...
Darien Springer's user avatar
0 votes
1 answer
64 views

Do software for creating Live Medias work whatever the CPU architecture of the target is?

So say with a software, you're flashing an image of Linux distro in a certain CPU architecture (say x86-32) to a USB drive & it's been know to work quite well. Then with the image of the same ...
kozner's user avatar
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2 votes
1 answer
787 views

Can one core perform several operations/instructions during one tick (because core has different execution units)?

A core has its own execution units and load/store buffers (additional "cache" - in addition to L1). Do those execution units have their own registers? Do cores also have their own dedicated registers?...
Code Complete's user avatar
0 votes
1 answer
66 views

Are there recent performance gains in virtualization by newer CPU generations?

I am using a workstation with Westmere Xeon CPUs and the performance I get in Virtual Box is a little bit disappointing. I have a Notebook at work with an i7-8550U at work which performs way better in ...
hex41's user avatar
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2 votes
0 answers
573 views

Armhf binaries on aarch64

So I'm running Arch Linux (64 bit) on a Raspberry Pi 3. What I'm trying to do is running a few BOINC projects on this machine. While some projects (like SETI@home) supply proper aarch64 binaries that ...
k8ieone's user avatar
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1 vote
1 answer
55 views

Spectre/Meltdown Windows vs. Ubuntu

I use a Notebook with an AMD E2-1800 processor which did not get any microcode updates. That means it is not quite protected against Spectre/Meltdown. In Ubuntu there is a very well explained wiki ...
Alex's user avatar
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7 votes
1 answer
10k views

Change CPU MHz from Registry

Is this safe? I was interested about the CPU so I did a little digging and found this location Computer\HKEY_LOCAL_MACHINE\HARDWARE\DESCRIPTION\System\CentralProcessor\0 ~MHz shows your MHz in ...
Ryan Smith's user avatar
0 votes
1 answer
47 views

What are some points to be kept in mind before installing ram sticks of different sizes? (2Gb + 4Gb)

My older Desktop had a 32bit Windows 7. But since the processor was 64bit capable, I dual booted it with a 64bit Windows 7. I want to upgrade the RAM to 6Gbs by installing another 4Gb RAM stick. I ...
Rahul Bhatt's user avatar
1 vote
1 answer
3k views

How does CPU/DMA access hard disk?

Considering x86 CPU / LINUX I want to understand how does cpu or dma access the hard drive ?does hard drive have to be accessed through IO Port addresses or it has to mapped into the memory (MMIO) ?
Usr1's user avatar
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0 votes
1 answer
289 views

How the speculative load and store happen in modern Intel processor?

I think the store queue is used in modern Intel processors for storing both memory address and store data. They do not go to L1 cache till the commit stage. But I am not 100% sure if it is correct or ...
world_of_science's user avatar
-2 votes
1 answer
393 views

How does multicore CPU thread synchronisation work at the hardware level?

I'm trying to understand how multicore CPU's implement thread synchronisation at the hardware level. From my research so far I've found that the process involves using a location in memory to act as ...
MSD's user avatar
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3 votes
2 answers
3k views

Virtualization not supported when attempting to run Docker for Windows on an AMD C-60

My Acer Aspire One, model AO725, doesn't support virtualization technology. Is there any alternative way to run Docker for Windows in this case? Processor: AMD C-60 APU with Radeon(tm) HD Graphics 1....
Azi_bel's user avatar
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0 votes
1 answer
126 views

Instruction set and pseudo-command

I use 'objdump' on linux in a variety of binaries and it returns their assembly. The commands that I receive is 'real' commands or pseudo-command? I have read that there are some commands which are a ...
0sunday's user avatar
5 votes
1 answer
2k views

Does TSX-NI provide an advantage when running virtual machines? [closed]

My question is about CPU architecture and the instruction set extension TSX-NI. For which usage scenario is it useful, and especially is it useful for web development or running virtual machines and ...
ihmels's user avatar
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0 votes
1 answer
170 views

Optimal CPI calculation confusion

I am reading https://insidehpc.com/2017/07/cycles-per-instruction-matters/: For example, if a certain part of the code takes 1200 cycles and executes 600 instructions, then the CPI would be 1200/...
Wad's user avatar
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0 votes
1 answer
193 views

Creating vCPU to physical CPU?

Say I have 8 core physical CPU system which supports hyperthreading which is mapped to 16 vCPU. Is it possible to configure increase or decrease the vCPU to 24 vCPU or 12 vCPU or this setting/...
user3198603's user avatar
0 votes
2 answers
2k views

Does conversion from assembly language to Binary language take place during decode stage in a processor?

I am newbie to computer science and here's what I think goes on in the FDEW cycle in a processor, 1.Fetch the instruction in assembly language 2.Decode to Binary language 3.Perform execution 4.Write ...
sham's user avatar
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