Questions tagged [cpu-architecture]

CPU Architecture refers to a collection of parameters about the design of CPU realized by its manufacturer, such as: its bit-ness or data bus width (16, 32, 64 bits) , Instruction Set (RISC, CISC,...), Memory Management, Threading, Virtualization support, etc

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What was the need to create different processor architectures? [closed]

I have been studying processors for a while and I found out that there are a lot of processor architectures available. Once we got a working processor architecture, why did we create other ...
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CPU max utilization limited to 1/N CPU’s for MOST multi-threaded Apps on any Win OS : WHY?

I understand multi-threading and tasking to some extent but know that outside of the OS, most Windows Apps are limited to using only 1/N CPU’s for averaged max. utilization. That is 50% for a dual ...
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Why aren't CPU instructions decoded before the program runs?

What is it about the decoding step of the instruction cycle that prevents it from being done ahead of time? The Intel 64 manual says things like "decodes instructions into micro-operations". ...
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Calculate upper memory limit of M1 chip [duplicate]

Why the M1 chip memory limit is set to 16GB,it is mentioned here that it is based on 64 bit ARM architecture, shouldn't it share the same memory limit which is 16 Exabytes? According to the linked ...
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Will Python be able to run on the new Apple machines running with M1 CPUs? [closed]

I am getting the new Apple MacBook with its ARM processors. I am wondering if Python will be supported on this new line of Macs. If it is not supported yet, then when will it be supported?
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Clock performance reduction in CPU

I am building a project requiring a lot of CPU power. I am currently having an AMD Ryzen Threadripper 1920X with 12 cores, 24 threads, each core running at 3.5 GHz. I am thinking about building a ...
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How can I find my computer's address bus width and data bus size?

I have a 64 bit x86 (x86-64) computer. Does that mean my address bus is 64 bit? I am trying to calculate addressability and address space as explained here. I don't really have any clue how to find my ...
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Where are the actual bytes located within DIMM modules in dual or multi-channel mode? [duplicate]

I'm trying to find out how memory is arranged in dual channel mode, i.e. which memory addresses are on which DIMM. What I have currently found out is that there are two modes "ganged" and &...
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Privilege levels in 64bit Intel architecture [closed]

I'm currently reading this paper and while this is probably a very basic question, I can't find an answer: In the Privilege Level chapter, how does the CPU know in what privilege level it's currently ...
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Do Operating Systems need to know which is the hardware architecture on which they are executing?

Maybe this is a basic theoric question, but I have no idea of the answer and haven't found information of this. Do Operating Systems (imagine Windows or Linux distros) need to know if they are ...
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Where does the “2” in 2^n come from when computing max memory size? n=n-bit

So I was reading up on address buses and max memory sizes, so my question is, when computing max memory size for any architecture, where does the 2 in 2^n where n is the address bus bit size come from?...
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GPU cores vs. CPU cores

A (say NVidia) GPU is made of streaming multiprocessors consisting of arrays of streaming processors or CUDA core. There are 5120 CUDA cores on V100. A general purpose (say Intel) CPU has "only" up to ...
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running an existing system based on i686 Centos 6 on a 64 bit architecture

I want to run an old Centos 6 based program (i686) on my Core i5 CPU but it doesn't seem to work although I have enabled virtualization. It's a pretty complex system with lots of software libraries ...
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How the CPU determines whether to put data in L1i or L1d

How does CPU decides what cache to use to store data just retrieved from memory? As far as I know the smallest unit of memory that CPU can access (read or write) is 64 Bytes (x86_64, DDR3/DDR4) which ...
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Does the instruction register have to send its memory address to MAR before accessing memory?

I am studying computer systems and operating systems and I have been confused about when a memory address would be transferred to the memory address register (MAR). When the instruction register (IR) ...
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Do software for creating Live Medias work whatever the CPU architecture of the target is?

So say with a software, you're flashing an image of Linux distro in a certain CPU architecture (say x86-32) to a USB drive & it's been know to work quite well. Then with the image of the same ...
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Can one core perform several operations/instructions during one tick (because core has different execution units)?

A core has its own execution units and load/store buffers (additional "cache" - in addition to L1). Do those execution units have their own registers? Do cores also have their own dedicated registers?...
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Are there recent performance gains in virtualization by newer CPU generations?

I am using a workstation with Westmere Xeon CPUs and the performance I get in Virtual Box is a little bit disappointing. I have a Notebook at work with an i7-8550U at work which performs way better in ...
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Armhf binaries on aarch64

So I'm running Arch Linux (64 bit) on a Raspberry Pi 3. What I'm trying to do is running a few BOINC projects on this machine. While some projects (like SETI@home) supply proper aarch64 binaries that ...
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Spectre/Meltdown Windows vs. Ubuntu

I use a Notebook with an AMD E2-1800 processor which did not get any microcode updates. That means it is not quite protected against Spectre/Meltdown. In Ubuntu there is a very well explained wiki ...
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Change CPU MHz from Registry

Is this safe? I was interested about the CPU so I did a little digging and found this location Computer\HKEY_LOCAL_MACHINE\HARDWARE\DESCRIPTION\System\CentralProcessor\0 ~MHz shows your MHz in ...
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What are some points to be kept in mind before installing ram sticks of different sizes? (2Gb + 4Gb)

My older Desktop had a 32bit Windows 7. But since the processor was 64bit capable, I dual booted it with a 64bit Windows 7. I want to upgrade the RAM to 6Gbs by installing another 4Gb RAM stick. I ...
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How does CPU/DMA access hard disk?

Considering x86 CPU / LINUX I want to understand how does cpu or dma access the hard drive ?does hard drive have to be accessed through IO Port addresses or it has to mapped into the memory (MMIO) ?
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How the speculative load and store happen in modern Intel processor?

I think the store queue is used in modern Intel processors for storing both memory address and store data. They do not go to L1 cache till the commit stage. But I am not 100% sure if it is correct or ...
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How does multicore CPU thread synchronisation work at the hardware level?

I'm trying to understand how multicore CPU's implement thread synchronisation at the hardware level. From my research so far I've found that the process involves using a location in memory to act as ...
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Virtualization not supported when attempting to run Docker for Windows on an AMD C-60

My Acer Aspire One, model AO725, doesn't support virtualization technology. Is there any alternative way to run Docker for Windows in this case? Processor: AMD C-60 APU with Radeon(tm) HD Graphics 1....
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Instruction set and pseudo-command

I use 'objdump' on linux in a variety of binaries and it returns their assembly. The commands that I receive is 'real' commands or pseudo-command? I have read that there are some commands which are a ...
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Gives TSX-NI an advantage for running virtual machines? [closed]

My question is about CPU architecture and the instruction set extension TSX-NI. For which usage scenario is it useful, and especially is it useful for web development or running virtual machines and ...
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Optimal CPI calculation confusion

I am reading https://insidehpc.com/2017/07/cycles-per-instruction-matters/: For example, if a certain part of the code takes 1200 cycles and executes 600 instructions, then the CPI would be 1200/...
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Creating vCPU to physical CPU?

Say I have 8 core physical CPU system which supports hyperthreading which is mapped to 16 vCPU. Is it possible to configure increase or decrease the vCPU to 24 vCPU or 12 vCPU or this setting/...
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Does conversion from assembly language to Binary language take place during decode stage in a processor?

I am newbie to computer science and here's what I think goes on in the FDEW cycle in a processor, 1.Fetch the instruction in assembly language 2.Decode to Binary language 3.Perform execution 4.Write ...
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Linux : Understanding load average and % CPU?

When I execute top command on my ubuntu system I see below results top - 07:58:58 up 1:21, 1 user, load average: 0.82, 0.73, 0.55 Tasks: 293 total, 1 running, 292 sleeping, 0 stopped, 0 ...
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How is the micro-op cache tagged?

According to Real World Technologies’ article on “Intel’s Sandy Bridge Microarchitecture”: “Sandy Bridge’s uop cache is organized into 32 sets and 8 ways, with 6 uops per line, for a total of 1.5K ...
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Find core used from CPU utilization?

I have average and peak CPU utilization(in percentage) of a linux server with me . Mainly couple of web apps are deployed on the machine. I need to decide what AWS machine suits me based on that. AWS ...
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How to make a 32-bit program from a 64-bit version?

Many software only supports 64-bit machine because the market for 32-bit is small now. However, for those who are stuck with 32-bit machines, this means newer versions cannot be installed, and this ...
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How to do measure execution time of cpu?

I want to measure execution time of cpus and compare them like bencmark websites. as I know we have a formula for the calculate that. Execution time = CPI * I * 1/CR But I stuck at the formula. I ...
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In Linux, is concept of Process similar to Container (in microservices?) [closed]

Process is executing an instance of an application. Every process got its State, ID, address space etc, and isolated to each other. It looks similar to Container that runs a specific service? In some ...
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Do process switch between different cores?

Will a process switch between different cores to increase performance? If the process does jump between cores, which components are shared across cores? L1-L3 cache, registers or memory?
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CPU usage by CPU component

CPUs are made up of multiple components, such as the ALU and CU. Hyper-threading allows multiple threads to run conconcurrently where there's available resource in these components. On a single core ...
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pthread_attr_setaffinity_np and logical core

I am a bit confused about CPU logical cores and physical cores and scheduler affinity. Let's assume there is a 4 physical core CPU where each core supports 2 hyperthreads. Henceforth, according to /...
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How are decimal operations calculated?

I understand the regular CPU does arithmetic for whole number types (e.g. integers) as well as bitwise operations; the FPU does floating point arithmetic. However I'm trying to learn how/where does ...
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Windows 10 CPU speed command

What is the command-line command I could use and get the CPU speed specifications? If there are options to also get other CPU specs I could use that too if someone could explain it to me.
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Why wouldn't security flaw affect AMD processor?

According to this news article there's a newly found security flaw in processors. However, the article also claims that it only may affect Intel processors and not AMD ones. I thought they were using ...
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Which measur unit process cycle in processor? [closed]

i have this question in my exam Process cycle in processor measure by: A) pulse. B)Rate C)cycle D)time Which one is correct! Thank's
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How to run executable without specific CPU flags?

I'd like to test the behavior of an Linux ELF executable on a processor that doesn't have some CPU flags such as aes and sse2 given a processor that has those flags. What is the simplest way to ...
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What is DEP, and how do I find out if my processor supports it?

Coreinfo shows me a bunch of instructions my processor supports. However one that I'm interested in is DEP Data Execution Prevention. DEP is listed as something the CPU must support in Windows 2016 ...
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Is there a way to tell if my hardware supports specific instructions? [duplicate]

Microsoft says, for Windows 2016 Server, Minimum: 1.4 GHz 64-bit processor Compatible with x64 instruction set Supports NX and DEP Supports CMPXCHG16b, LAHF/SAHF, and PrefetchW Supports Second Level ...
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What is the importance of clock in flipflops

I understand that the difference between latches and flipflops that the value stored in flipflops can be changed on pulse only in clock intervals. But what is the real need to do it? I mean if value ...
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Why Hyper-Threading provides 2 virtual cores but not more?

Here is an explanation of Hyper-Threading found on Wikipedia: For each processor core that is physically present, the operating system addresses two virtual (logical) cores and shares the workload ...
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x86/amd64 architecture Malware on ARM architecture malware Detonation

Situation: Thinking of making a malware detonator using an ARM single board computer, which has a file scanner in it. Problem: I am scanning computers (x86 and/or amd64), therefore malwares will be ...