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I'm doing research into novel Computer architectures and I need a clearer picture of how Memory Control works in a PC.

In short, I would like to know whether a PCI-E device, such as a GPU can access RAM and write to RAM without having to contact the CPU. Assume that the system knows where it is allowed to write to (kinda like a Virtual Machine), so that your system does not go haywire.

A short clear description of how the memory controller and CPU interact and how GPU's or PCI-E devices access system memory would be greatly appreciated.

Thank you in advance, Gecko

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    DMA has been supported on even ancient motherboards.
    – Ignacio Vazquez-Abrams
    Oct 17, 2015 at 21:04
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    In a lot of modern systems the memory controller is part of the CPU ...
    – PlasmaHH
    Oct 17, 2015 at 21:04
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    There is a difference between DMA and Bus Mastering. It sounds like this question refers to the latter (transfer initiated by the peripheral, not a device driver running on the CPU).
    – David
    Oct 17, 2015 at 21:58
  • Read ertl.jp/~shinpei/papers/icpads13.pdf
    – the gods from engineering
    Oct 17, 2015 at 23:13
  • If you consider the on-die memory controller is not part of the CPU, in which case, yes.
    – qasdfdsaq
    Oct 18, 2015 at 19:56

2 Answers 2

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In a word, yes. Originally ( in the 8086 ) it was called DMA, or Direct Memory Access. Back then there was a dedicated DMA controller chip that the CPU had to program to transfer data between ram and peripherals, but at least as far back as the early PCI days ( and I think on the original ISA bus too, but I don't know of any devices that did ), peripherals themselves could also be bus masters, and transfer the data themselves.

They still normally require the cpu to tell them what parts of memory they should access, but some badly behaved devices, such as firewire controllers, open up DMA access to all of the system's ram at the behest of some external device on the firewire bus. Some modern PCIe systems have smart PCIe bridges that can be programmed to perform address translation and access restrictions so the CPU can prevent devices connected behind them from accessing memory they shouldn't, but this currently seems restricted to big server type motherboards, not your typical desktop.

As for how, the PCI(e) bus allows any device to perform read/write to any address, be it in the main system ram ( typically controlled directly by the CPU these days ), or on some other device on the bus. That is, one PCI(e) device can directly access the memory or registers of another PCI(e) device, or main system ram, without regard to where it is located. The PCI(e) bridges route the request to the appropriate device, as they are configured ( by the system firmware/bios, and possibly later by the OS kernel ) to know what address ranges are "owned" by what device.

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  • As for the original ISA bus. An Example is the Adaptec 1542CF SCSI hostadaptor. (16 bit ISA).
    – Hennes
    Oct 18, 2015 at 17:12
  • Hard to find a reliable citation, but serial ports using the 16550AFN UART supported DMA transfers. It looks like serial ports interfaced with the CPU via the ISA bus (this part is hard to cite). People old enough to remember when 14400 bps modems were the rage will remember that 16550A (at least) was pretty much a requirement, due to bugs in earlier UARTs.
    – ChrisInEdmonton
    Oct 18, 2015 at 23:22
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    @ChrisInEdmonton, yea, I remember the 16550A ( also was great because it had a 16 byte FIFO ), but never heard of the AFN.
    – psusi
    Oct 18, 2015 at 23:31
  • DMA already existed in the original IBM-PC architecture, with the ISA bus, like other architectures at the time, actually. So it's really an old concept. Don't you remember old soundcards on ISA slots required you to manually configure which DMA channel to use? Since no configuration was automatic back on those days, it's easy to remember (the pain).
    – Johan Boulé
    Sep 25, 2016 at 20:10
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I would like to know whether a PCI-E device, such as a GPU can access RAM and write to RAM without having to contact the CPU.

Yes, it is called bus mastering.
The PCI/PCIe adapter can gain control of the bus, and compete for memory cycles. The CPU, the DMA controller and bus masters could all be competeing for memory access. The memory arbiter typically favors the CPU, which is typically assigned the highest priority.

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